Due to the increased portion of static random access (SRAM) arrays in the total chip area, device dimensions in SRAM must be continuously scaled. With shorter device channels and widths, the intrinsic device fluctuations and random mismatch among adjacent devices are significantly increased due to random doping fluctuations, short-channel effects, and narrow-width effects. Thus, the stability of SRAM degrades with technology scaling. Random doping fluctuation (RDF) is a major source of variation for SRAM circuits. Using an un-doped body with back-gate biasing in Fully Depleted Silicon-On-Insulator (FD/SOI) or double-gate (DG) devices, as set forth in H. Ngo et al., VLSI-TSA, pp. 147-148, Taiwan, April 2006, can reduce RDF. However, FD/SOI needs a thin buried oxide layer (BOX) for back-gate biasing, which increases the bit-line capacitance and degrades the performance. Local biasing methods for independent-gate controlled double gate (DG) SRAM cells increase the cell area.
In summary, with regard to prior-art approaches, the conventional scaled symmetrical six-transistor (6T) cell is not stable, employing FD/SOI SRAM cells with back-gate biasing degrades Read performance, and using independent-gate controlled DG SRAM cells increases the area.